1. Field of the Invention
The present invention relates to a technique of handling design data of a pattern of a semiconductor device and, more particularly, to a pattern forming method and a pattern verifying method which efficiently and uniformly process a series of processes according to data design of the pattern.
2. Description of the Related Art
In recent years, micropatterning and high integration density of a semiconductor device are conspicuous. Accordingly, when process simulation is performed on design data of a pattern designed in conformity with a design rule, although optical proximity correction (OPC), a resolution enhanced technology (RET) process and the like are performed, process dangerous portions where patterns are connected to each other or disconnected from each other at unexpected positions, or line widths or space widths of patterns not satisfying regulated conditions are occasionally found. The following method is disclosed in, for example, Jpn. Pat. Appln. KOKAI Publication No. 2005-181524. That is, with respect to process dangerous portions, at least one of a design rule (DR), a process proximity correction (PPC) parameter, and a semiconductor manufacturing process parameter is repeatedly optimized to create a guideline for changing a design pattern or a layout, and on the basis of the created guideline for changing the design pattern, the design pattern and the layout are partially modified.
For verifying whether a result obtained by partially modifying the design pattern or the layout is correct, several methods are known. For example, it can be automatically verified by performing a design rule check (DRC) as to whether a design rule is satisfied. In addition, it can be automatically verified by a process rule check (PRC) using a process simulator or the like to check whether a dangerous portion predicted on the process is eliminated.
However, even though these verifying methods are used, it cannot be verified whether input design data is correctly modified on the basis of a guideline for modification. More specifically, when a design rule check, process rule check and the like are performed, even though a modification result satisfies the design rule and passes these checks and the predicted process dangerous portions are eliminated, it is impossible to detect the danger that the pattern and the layout might be modified by an unnecessarily large amount of modification in comparison with the pattern and the layout intended by a designer. Since a design target itself is modified by the above modification method, verification performed by “comparison with target” as a general verification cannot be performed, and the propriety of the modification cannot be easily verified.
To satisfy the request of improving the yield, the pattern and the layout may be modified while partially outstripping the design rule to preferentially avoid dangers in processing. In this case, the pattern and the layout are modified on the basis of a guideline for modification which partially violates the design rule. As a result, when a portion which is unexpectedly modified or a portion which is fatally modified is not detected by the process rule check, the modified portions cannot be detected.
In this manner, according to a conventional technique, when design data and a design layout of a pattern initially input in a pattern design process are unexpectedly modified, these modified portions cannot be automatically detected. For this reason, the step of visually verifying modified portions one by one is necessary. The pattern design process thus requires a lot of time and enormous cost. In addition, since criteria for determining pseudo errors and true errors depend on the verifier, mask data having uniform quality cannot be easily created.